Most digital circuits on the market are tested by their manufacturers several times before they are delivered. Component testers are assigned to generate digital signals (logic "0" or "1" states) and to verify the presence of transitions at the output of the circuit under test. The signals generated and the comparison signals are programmable both in time and in level. A component tester must generate and/or compare signals on all of the function pins of the component under test simultaneously.
Defining the signals to be generated and/or to be compared is generally extremely complex. Testing a microprocessor can give rise to strings of several million zeros and ones in the same sequence. To define such signals, the notion of period is used to define a time slice within which a more simple signal is described. Such a signal is subdivided into an item of time information (also referred to as a "time marker") and an event (e.g. a transition or a test).
Executing a functional test thus results in a memory running in which each line corresponds to a period and whose content represents the time information and the events defining the signal within the period for each pin. In addition to the time information and the events, there is an instruction serving to manage the running of the memory. The instruction is common to all of the function pins of the circuit under test. The most commonly used instruction is the instruction consisting in going to read the following line (INC instruction). This memory is referred to as the "main" memory. "Sub-program" memories are also used.
This architecture, based on running the memories, is deterministic, i.e. the architecture assumes that it is possible, a priori, to know exactly what is going to happen at a given instant on the output pins of the circuit under test.
Digital components (e.g. microprocessors) exist in which the internal logic state cannot be known a priori. Therefore, the test signals cannot be known a priori. To test this type of component, it must be possible to bring the component into a known state. For this purpose, it must be possible to generate signals (e.g. clock signals) until a predetermined event or succession of events appears on one or more outputs of the circuit under test. To manage the running of the main memory or of the sub-program memory under such conditions, suitable instructions exist that consist in looping the memory so long as a particular condition has not occurred. The method which consists of waiting for a circuit to put itself in a predetermined state is called "matching". The simplest example is to consider a divider whose initial state is not known. Clock signals generated at the input of the divider cause a transition to occur once every n clock edges. To synchronize this type of component, it is necessary to generate clock signals until an output transition appears. Once such a transition appears, the divider is in a known state, and the remainder of the test is performed in deterministic manner. If the component under test is bad, the exit condition from the matching sequence might never be found. A maximum number of loops must be initially programmed to avoid looping indefinitely. For example, for a divider by n, the output transition must be found in less than n+1 clock edges. In which case, after n+1 edges, the matching sequence stops and the divider is deemed to be bad. In certain complex cases, the time necessary for deeming a matching sequence to be bad can be quite long.
The architecture of a tester contains a portion for generating/receiving digital signals and a portion for shaping said signals. Usually, the shaping portion constitutes the measurement head whereas the generate/receive portion can be situated in a separate bay.
To optimize the cost of the test, it is possible to connect a plurality of heads to the portion for generating/receiving signals. Generally, multiplexers (1 per signal and per pin) placed at the output of the generate/receive portion make it possible to switch the signals to one head or to the other. Thus, a component is tested on head No. 1 while another component is being connected to head No. 2, and vice versa. This makes it possible to increase the capacity of the tester by adding a head. Typically, if the test time is identical to the connection time, adding a head makes it possible to double the capacity of the tester. The circuits tested on the two heads must be identical.
Since identical signals are generated on both heads, and since the comparison signals must also be similar, it was decided to propose testers having two heads for simultaneous operation. The generated signals are sent in parallel to both heads. The received signals are compared with a table simultaneously by different circuits. The tester then handles two results: the result coming from head 1 and the result coming from head 2. Thus, merely by duplicating the circuit for comparing the received signals with a table (given that the table is the same for head 1 and for head 2 since the generated signals and the components to be tested are identical), the capacity of the tester is genuinely doubled.
Testing in parallel makes it possible to test n components simultaneously in a manner similar to testing a single component. The entire set of resources serving to test a component is referred to as a "site". Simultaneous testing may be performed on the same head or on a plurality of heads. The present invention addresses both of these cases.
When a plurality of components are tested in parallel, matching involves bringing all of the components into a known and identical state. When the desired condition appears on a first one of the components, the other components can be in any state. It is thus necessary to synchronize the first component, and then to go on to the next component while maintaining the first component in a known state and so on.
Conventional component testers suffer from a serious drawback which is that when a defect is detected during a functional sequence, the sequence is stopped, and, generally the next component is then tested. An object of the present invention is to provide method and equipment for testing in parallel, in which method and equipment good components continue to be tested while matching of bad components is ignored, so as to avoid having to devote time, and possibly a long time, to trying to synchronize a bad component.
Furthermore, it must be possible for a test designed to operate on n components in parallel to be capable of operating on a smaller number of components. According to the present invention, the matching sequences for matching a bad component or an unused site are automatically ignored so as not to penalize the test time. For example, when testing a silicon wafer, when the spike card arrives at the end of the wafer, it is possible that the sites are outside the diffused zone, and that certain test needles are not in contact with any of the components. In which case, a tester of the present invention ignores the matching sequences for such components.
The matching sequences may be ignored a priori if the corresponding site is disabled, or if another test has already deemed the component to be bad.
The matching sequences may also be ignored in real time if one of them does not succeed.